Re: [oc] Help: SDF Simulations

[Rudolf Usselmann <rudi@asics.ws>]

On Monday 03 June 2002 22:37, you wrote:
...
> Now comming to my problem: I used Xilinx-ISE-3.1i's Design_Manager
> to generate the SDF file. I got a *.v file and a *.sdf file. I
> used the *.v file in my simulation environment. Can any one help
> me out with the procedure to run this simulation, please? I target
> my design to xcv2000e-6bg560 device.

Depending on how the .v file was generated, you might need
the Xilinx Verilog libraries. Just do a search where you installed
your xilinx tools for .v files. It's somewhere in a "simprims" directory.
You need to tell your Verilog simulator to search this directory for
library primitives (usually done with the -y switch). BTW: It would
help if you would tell us what tool you are using for simulations.

Then you need to tell your simulator to read the sdf file. This can
be done in the top level of your test bench by something like:

initial  $sdf_annotate ( "<sdf_file_name.sdf>");

Depending on your simulator, you might have to pre-compile the
sdf file.

Try to RTFM.

Hope this helps,
rudi
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>
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