I think in the file wb_dma_wb_if.v, there is an error. A slight typo lead to the master data being connected to slave and vice versa. The lines 175/176 and 202/203 should be swapped. This lead to a completely non-functional controller. This should fix it. Has anyone noticed this before? -- To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml