RE: [oc] oc8051

["Taiyi Cheng" <taiyich@palmmicro.com>]

I am trying this core recently, seems the port mux (P0, P1, P2, P3) is not
considered.

Also, of the documents can include the structure description, it will be
helpful for others to test and debug.

thanks.

Taiyi

-----Original Message-----
From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On Behalf
Of simon.teran@campus.fri.uni-lj.si
Sent: Saturday, December 15, 2001 10:58 AM
To: cores@opencores.org
Subject: [oc] oc8051


Hi

I updated oc8051 home page (www.opencores.org/projects/8051). You can find
there current version. Basic CPU core is done. Some peripheral modules still
missing (interrupt controls, timer/counters and uart).

Since i'm new in HDL design, I'll be wery happy if someone would look my
core
and mail me opinion.

regards,
simon
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