Any idea about DES core in VHDL ? I run around opencores.org but found only in Verilog version. MangMug -- /* ___ ^ \e/ | | /e\ v --- Erik M. Sirikhum, OpenSource Designer, Eric Conspiracy Secret Labs <s2010159@kmitl.ac.th, s2010159@ce.kmitl.ac.th> http://chaokhun.kmitl.ac.th/~s2010159 */ -- To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml