RE: [oc] RS232 SYS CON

["Igor Mohor" <igorm@opencores.org>]

Yes, it comes to 320 or 0x140.  Fclk/(16*lowest_rate)=320

 

For 30 Mhz the divider would be: 195 (0xc3)

 

Regards,

    Igor

-----Original Message-----
From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On Behalf Of Shehryar Shaheen
Sent: 30. januar 2002 15:40
To: cores@opencores.org
Subject: [oc] RS232 SYS CON

Looking for John Clayton authour of the rs232_sys_con core but if any one else can answer that is just as fine.

 

Hi John,
           I intend using your core in a network controller that I am designing , I'll be using a 30 MHz clock.

 

 I have gone through the documentation os RS232_SYS_CON but the example given has probably a typing error

 

followning I have taken out of the comments in serial.v

 

clock_factor=16
lowest_rate=9600
Fclk=49.152 MHz

 

clock_factor*(Fclk/lowest_rate) = 320 <-- How this comes to be 320  with the above values

 

I have a 30 MHz oscilator on board and would appriciate your help! also is the code available in VHDL as well.

 

Thanks

 

Shehryar Shaheen
PEI Technologies
University of Limerick
Ireland