AW: [oc] Visual VHDL.

["Robert Taubner" <robert.taubner@sigmatek.at>]

I am working with HDL Designer from Mentor Graphics, which is like a CASE
tool. Maybe this is what you are looking for.

Regards

Robert Taubner

-----Ursprungliche Nachricht-----
Von: owner-cores@opencores.org [mailto:owner-cores@opencores.org]Im Auftrag
von Jean Masson
Gesendet: Montag, 28. Janner 2002 17:18
An: cores@opencores.org
Betreff: Re: [oc] Visual VHDL.

Hello all,

I know that graphic is an antinomic concept in VHDL. Meanwhile, a form of
graphic components, wich
are inside
cores of Visual C++, C++ Builder or Delphi, should be useful in a VHDL
context. FPGA Express has
this sort of idea in his
entity wizard, where you obtain an entity as a result of graphical
definitions of signals. I wish a
sort of integration of VHDL GUI
in current development systems, a CASE graphical tool in parallel with a
textual language. A
graphical expression of top-down
hierarchy should prevent errors, or confusions, in names of signals in
complex projects.

I have heard of Pictorial VHDL, an hybrid of VHDL and Pictorial JANUS. But,
after a mail at
Paderborn University,
it seems that the project has stay virtual.

I want to know if anybody as heard of a sort of Visual VHDL, in a future
ANSI norm for the language
or without any
normalization. In a search with Google, I have seen 49 occurences for key
"Visual VHDL", so I am
not the sole guy
in the world thinking at this concept.

Best regards,

Jean MASSON

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