Re: [oc] Binary Divides for uP core

[Jean Masson <Jean.Masson@lium.univ-lemans.fr>]

Hello Paul,

I use a book of Niklaus Wirth wich gives the architecture and synthesis listing of integer 8 bits
multiplier and divider.
HDL used in the book is Lola, a language created by N. Wirth. It is relatively easy to translate
Lola files to VHDL or Verilog.

The name's book is approximately : Introduction to logic synthesis for computing students. Springer
Verlag editor.
This is a fine book, full of informations for logic synthesis biased guys.

It is not possible, at my knowledge, to do division in one cycle. This is typicaly an iterative
process. You must evaluate in
parallel 2 integer numbers : result and rest. Division is not like multiplication, that is
implementable in pure combinatory logic.
In DSPs, multiplication is performed in 1 cycle, division takes allways a number of cycles equal to
its format.

Wirth uses a sequential process with conditional substraction of a shifted word. A 8 bits word is
divided in 8 cycles.
If you use a combinatorial multiplier, an SAR register could gives you the result, like SAR of ADC.

Another method is an approximation by Newton's algorithm. You search by iteration the inverse of
divider and do
multiplication with inverse : A/B = A*(1/B). Consult the old Data Book on AMD2901, where I have
found the idea.

If you find THE trick (the divider of  McFeeters) to do division in 1 cycle, please give us a mail
with the description
of your method.

Best regards,

Jean MASSON


> On Tuesday 15 January 2002 04:30 am, Paul McFeeters wrote:
> > Hi,
> >
> > Does anybody know the routine for doing a binary division in HDL?
> > I'm developing a uP core and would like to do divisions in one
> > clock cycle if possible? The multiple instruction was easy to
> > figure out but I'm still stuck on the division one.
>
> > Paul
> --

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