[oc] how to accomodate slower and faster modules in your design

["Umair Farooq Siddiqi" <ufarooq.geo@yahoo.com>]

hello

Iam designing parallel pipelined modular multiplier for RSA
encryption.decryption process. My design uses 32 words configurable Look up
table for modular reduction. The table should be reconfigured for a change
in mod value. The mod value can only change before or after a complete
encryption process. On the basis of speed requirements I divide my design
into two parts:
1.Modular Multiplication module. That will actually do modular
multiplication. It's pipelined with a combinational logic delay of
(10-12)delta between each pipeline stage. I used carry select adders and
other techniques to limit the delay to this limit.
2. The second part is the reconfiguration of the Look up table, I want to
design it a resource efficient. pipelining and speed are not very important
here. Now if i make it non pipelined or set larger combinational logic delay
between pipelined stages Does it effect the clock of my faster circuit ?
Does it slows down my whole design ? Can you advice me using a clock divider
for the slower circuit ?


Thank you.

Umair
EE student
NED UET
Pakistan


--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml