RE: [oc] Re: How to create such signal wave using VHDL?

["Paul McFeeters" <paul.mcfeeters@ntlworld.com>]

Marko,

find a opencore for Ethernet, implement it and then use the TCPsocket implementation
off a copy of Linux and translate the C into Verilog (or VHDL if you are brave).
Not bad for 10seconds of thinking egh? Anything I missed?

Paul

> -----Original Message-----
> From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On
> Behalf Of Marko Mlinar
> Sent: 20 December 2001 14:33
> To: cores@opencores.org
> Subject: Re: [oc] Re: How to create such signal wave using VHDL?
> 
> 
> > for my 2pence worth, I know people have done a combined Ethernet and
> TCP/IP stack in a
> > single FPGA which I think is pretty cool. Although they did 'cheat' and
> used a C to netlist
> > compiler instead of Verilog but if you are up for a challenge I think its
> a neat idea. Given
> > the popularity of TCP/IP these days it would give you a nice boost when
> they ask you at
> > interviews "do you have any experience of TCP/IP?".
> How much time you think one person would need to finish such project?
> 
> Marko
> 
> 
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