[oc] Verilog vs VHDL

[brad@tinyboot.com]

Since some cores on Opencores are expressed in VHDL and 
others are expressed in Verilog, I'm wondering which language I 
should code new hardware in. I know VHDL but maybe Verilog 
would be more productive. 

How good a job do translators do when going from one language 
syntax to the other. I would like to start with a source language 
that translates in the least messy way.
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