Re: [oc] New 64bit instructions for 32bit processor cores analogy

[Steve Wilson <stevew@intrinsix.com>]

Paul,

Three data points for you - ARM has both a 16 and 32 bit instruction set.
The Tensilica processor has a variable instruction set from 16 to 32 bits depending on what it's
doing.
The ULTIMATE variable instruction set machine was the Burroughs B1700 which could vary it's data
path from 1 bit to 24 bits in length. It was used as a platform to run interpreters, used
self-modifying code on purpose in same (makes GREAT computed gotos when you can OR in to the
instruction word on the fly) The interpreted languages it ran used huffman encoded word lengths
for the different instructions to save memory.  An MOVE instruction would be MUCH shorter than a
square-root instruction. (I worked on this one too ;-)

Steve Wilson

Paul McFeeters wrote:

> Dani,
>
> Wouldn't matter much on my PC, disk access is so slow I sometimes wonder
> whether I'm accessing the floppy or not. Gotta love Win98, when I dual
> boot to Win2K the same performance program rates the same drives at
> 5x faster. Good old Microsoft, now where did I leave my voodoo doll?
>
> Yes a variable length instruction is possible and available commercially.
> www.motorola.com/coldfire products use it. They call it VL-RISC which
> presumably stands for Variable Length RISC. Looked at using their CPUs
> in some projects briefly before I discovered FPGAs. They are aimed at
> SoC type areas hence the processors have everything up to and including
> Ethernet/USB ports on them. Harvard memory architecture, built-in DRAM
> controllers (except the lower 2 models) and other things. It might have
> even have a 10 stage pipeline, 10 blocks in the diagram anyway ;-)
>
> Still working on the computer with a CPU core for the Linux project so
> maybe crack that one when I can devote some time to it. :)
>
> Paul
>
> -----Original Message-----
> From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On
> Behalf Of Daniel Haensse
> Sent: 11 December 2001 12:38
> To: cores@opencores.org
> Subject: Re: [oc] New 64bit instructions for 32bit processor cores
> analogy
>
> Paul,
>
> the problem will be that your harddisk will swap 4x as much and read/write
> larger data or code from the harddisk. What do you think about a variable
> instruction length, instead of a fixed 64 bit length? Is this possible?
>
> Dani
>
> --
> To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml

--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml