RE: [oc] Sequential processing in VHDL? Whats the best way to do it?

["Paul McFeeters" <paul.mcfeeters@ntlworld.com>]

Martin,

> Clocked processes tend to follow the template
> process(clk, resetn)
> variable PC: integer range 0 to some_big_number;
> begin
>  if resetn = '0' then
>    PC := 0
>     -- initialise lots of variables
>  elsif rising_edge(clk) then
>     case PC:
>       when 0 => --do something
>       when 1 => do something else
>     end case;
>    PC := PC + 1;
> end process.

> This will again create very deep logic, but may work.

> My thought would be to create one of these for each section of code that
needs to have
> "sequential" behaviour.  Each section will then operate in parallel as
signified by the
> par{} constructy in Handel-C.  Or >however you choose to express
paralellism.

Your code is so close to the one I did its freaky, did I leave my webcam on
pointing at
the screen? lol I tried it with 8 instructions (similar to FSM-8) in VHDL on
Webpack.
Programmed the off chip to 4MHz. then clocked this  down to 1Hz
(std_logic(22) of counter)
and then used this 1Hz clock for my 'process code' so I could watch the LED
change. In one
'instruction' block I switch the LED off and all the others turn it off.
Simple enough but I am well f***ed if I know what Webpack compiled it as!
The LED comes
on for a second, goes off for a second then on again etc...  I expected LED
on for 1 sec
then off for 7 then on again. How the hell does Webpack screw that one up?

> Which platform?  I may be able to test...

I am using XC2S200-5PQ208 chip on a Burch-Ed board (qu. = 2), alas Tony
didn't have any
8/10 LED segment or 7 segment displays left for his boards so I'm stuck with
just the
single display LED on the board. (I haven't looked at toggling the power
supply LED one
;-). I will probably wire up 16 LEDs onto another prototyping board just to
get a better
idea of how badly Webpack is messing up my code.

> Webpack is not a 'real' simulator AFAIK.  Xilinx and Altera both offer
limited versions of
> Modelsim, but I reckon you'll reach the 500 line limit fairly quickly.
There are some free
> (for some senses of the word) simulators about, which I think are text
only, but that may
> be fine for a start off.  Esp. if you get printf's in there!

Aaaaaaaaaaaah did you say 500 line limit? Forget that one then, that might
be one printf statement!
If my program could say compile my own version of C down to a .RBT file to
squirt into the FPGA
then I will be mightily pleased alas will still need some sort of "place and
route" software step.
Certain aspects of FPGA programming still seem way too expensive to me, most
notably the software!
But not for too long. ;-))

Just have to have words with Altera and Xilinx, whoever wishes to supply me
and my development
partners with proper development software and a budget board will be the
ones we develop the
code for. The 'loser' company can just wait for our program to support their
devices. I'm sure
that after spending $25,000 on software licences for the current programs it
doesn't leave a lot
of money for buying loads of development boards unlike when the software is
free leaving $25,000
for development boards and other things. Also when my software is released
into the world lots of
C programmers are suddenly going to be able to code directly into hardware.
If only 5% of all the
world's C programmers in the world needed to buy a FPGA development board
how many would that be?
Note to self, buy loads and loads of shares in whichever company gives me
development tools.

You in Solihull? I've been there at one time, can't remember why though.
Maybe on assignment or for an
interview. Could have even been a pub-crawl hence the haze.

Paul

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