[oc] VHDL help.

[Kausar Ahmed R <kausarahmedr@yahoo.com>]

Hello,

   Can anyone please tell me in detail ( & in simple terms ) what exactly the following VHDL functions do ?

Also, are they supported for synthesis, especially in Xilinx Foundation-F3.1i tool ?

Thanks in advance.

   Kausar.  [ kausarahmedr@yahoo.com ]

 

[1] FUNCTION to_high_imped(arg : bvec) RETURN bvec IS
          VARIABLE result : bvec;
      BEGIN
           FOR k in arg'RANGE LOOP
             CASE arg(k) IS
                  WHEN '0' => result(k) := 'L';
                  WHEN '1' => result(k) := 'H';
                  WHEN 'L' => result(k) := 'L';
                  WHEN 'H' => result(k) := 'H';
                  WHEN OTHERS => result(k) := 'Z';
             END CASE;
          END LOOP;
        RETURN(result);
     END FUNCTION to_high_imped;

---------------------------------------------------------------

 

   And the

 

[2] FUNCTION To_X01  ( s : std_logic_vector ) RETURN  std_logic_vector ;

 

 ( ieee, std_logic_1164 )

 

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