Re: [oc] A 'core server' ?

[John Dalton <john.dalton@bigfoot.com>]

> > > But why don't you use C?
> > 
> > 1) C is non-trivial to parse 
> The idea was very simple - to write C program which generates
> .v or .chdl file.

Actually, without realising it, I think we are almost in
agreement.  A C generator (unless it is a really simple one)
needs to keep a data structure in memory as it generates.  I
am proposing that this data structure be a heirarchy of linked
lists.  By another name, this is LISP/Scheme.

The full sequence of events would be:

C(or other language) -> Lists in memory -> VHDL or verilog

> :)
> Personally I don' t believe in C to verilog translators, since it
> is then quite impossible to generate good logic from HDL.
> Maybe for testbenches.

I suspect this short coming is a function of available tools,
similar to the fact that a few years ago, a 'good' design
was structural, not synthesised.  Of course this has changed
as synthesisers developed.  I agree that C (or similar language)->HDL
is currently lacking, but I assert (without any proof) that
this will be a temporary situation.

> If you want to use same RTL (register transfer language) tree
> representation as gcc uses internally, it is quite a lot of work to
> translate from verilog. How would you translate bunch of 
> always constructs? I suppose you need to make whole
> HDL simulation for that.

I am actually looking at a 'gcc tree' structure.  This is different
to RTL.  The (rough) sequence, as I understand it, is the source
gets translated to a tree, which then gets translated to RTL.
A tree is higher level than RTL.

You are correct in pointing out the difficulties in
translating structures which are simultaneously
executed.  This is something to be addressed.

> Of course, I was thinking of the same thing, but examples were
> very simple. Why can't you do this using verilog-2000?
> I would say, that Verilog generate statement is as powerful as C.
> You also have floating point.
> What do you think it is not possible to code?

My latest work has been in VHDL, so I will have to do a bit
more verilog-2000 reading before commenting on thjis one.


Best wishes
John
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