Re: [oc] I2C Core, SPI Core

[Richard Herveille <richard@asics.ws>]

>Hi folks,
>
>does anybody know how many gates the i2c wishbone core needs?

Well if anybody should know then it should probably be me right :-) ?

The i2c_wishbone_master uses approx. 250lcells for an Altera or 120CLBs for 
a Xilinx device

>I had a brief look at it and it is really more then just a 17bit shift
>register!!!!

Jee, ever saw any IP core around being just a shift register (besides being 
a shift register) ???

Richard

>I'm also looking for a SPI core, is there some vhdl code around?
>
>best regards
>
>Dani
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