Re: [oc] RE: Question on Block RAM

["MikeJ" <mikej@freeuk.com>]

Hi, you may want to do it like this (in VHDL at least):
bits in % are comments!
if you are being really clever you can use a function to take the
rom_name'INIT_00 etc attribute and convert it into a vector for the generic
map automatically, so you only have to type in the init attributes once. If
you don't need the simultation to be initialised you can cut out the bits
between the --pragma's (as thats what the synthesis tools do).

architecture RTL of FRED is
  attribute INIT_00 : string;

  %repeat for INIT_01 to INIT_0F%
begin

rom_name : if true generate
  attribute INIT_00 of char_rom_high : label is
"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF";
  %repeat for INIT_01 to INIT_0F%
  begin
  char_rom_high : RAMB4_S4_S4 % for example, see lib guide for others %
  --pragma translate_off
  generic map (
       INIT_00 =>
x"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF",
   %repeat for INIT_01 to INIT_0F%
        )
  --pragma translate_on
  port map (
    doa   => %signals%
    dia   =>
   addra =>
    wea   =>
    ena   =>
    rsta  =>
    clka  =>

    dob   =>
    dib   =>
    addrb =>
    web   =>
    enb   =>
    rstb  =>
    clkb  =>
    );
  end generate;

rest of code

or, in the UCF you just need

inst ROM_NAME INIT_00 =
0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF;
etc for INIT_00 to init_0F

Hope this helps,
regards

Mikej.

----- Original Message -----
From: "akhan" <akhan@iwavesystems.net>
To: <cores@opencores.org>
Sent: Thursday, August 30, 2001 11:39 AM
Subject: Fw: [oc] RE: Question on Block RAM


> > > ----- Original Message -----
> > > From: "Victor the Cleaner" <jonathan@canuck.com>
> > > To: <cores@opencores.org>
> > > Sent: Thursday, August 30, 2001 5:28 AM
> > > Subject: Re: [oc] RE: Question
> > >
> > >
> > > > > I am currently trying to initialize some Xilinx block-RAMs in my
> > Verilog
> > > code, using Xilinx Foundation 3.1i.
> > > > > I followed the instructions which say to use:
> > > > >
> > > > > file://synopsys attribute <name> <value>
> > > > >
> > > > > So, I ended up adding:
> > > > >
> > > > > file://synopsys attribute dp_ram_block_1/ram0/ram0/INIT_00
> > > "0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF"
> > > > >
> > > > > But it does not seem to work.  Does anyone have an example of
> > > initializing Xilinx BLOCK RAMs for FPGA Express or Xilinx FND3.1i?
> > > > > I am stuck.
> > > > >
> > > > > - John Clayton
> > > >
> > > > John:
> > > >
> > > > I haven't tried initializing the Block RAM from HDL, but I have
tried
> > two
> > > > other methods:  In Coregen and via the .ucf file.
> > > >
> > > > Doing it through Coregen is totally easy - you just tell it you want
> to
> > > > initialize the memory and specify the .mif file, which contains the
> data
> > > > in A Sensible Format.
> > > >
> > > > Don't get me started on doing it via the .ucf - it's total insanity.
> It
> > > > can be done, but you won't like it.
> > > >
> > > > This was under 3.1i, btw.
> > > >
> > > > Jonathan
> > > >
> > > > --
> > > > To unsubscribe from cores mailing list please visit
> > > http://www.opencores.org/mailinglists.shtml
> > >
> >
>
>
> > Hi John Clayton,
> >
> > You can use the core generator which comes with Xilinx FND3.1i. to
> generate
> > the Block RAM core and you can instantiate that core in your code.
> >  You can follow the steps given below if you are using verilog. VHDL
> should
> > be similar, but I have never used BLOCK RAM using VHDL earlier.
> > 1. From the Accessories of the Xilinx Foundation Series 3.1i, open the
> "Core
> > Generator System".
> > 2. Open your existing project or a new project.
> > 3. Select Stoage Elements and Memories in which a wide range of RAMs are
> > give. You select any of them and follow the tool to get the code for
> > instantiating BLOCK RAM.
> > 4. Take care about the "component name". It should be same as the one
> > present in \xilinx\verilog\unisims.
> > 5. instantiate the code generated in your code. Remember to include the
> > library file "RAMBxx" in your project directory.
> > 6. If you want some values in the BRAM at reset, you can initialize
using
> > .mem file, otherwise you can neglect it.
> >
> > Best of luck.
> > Karthik
> >
>
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
>
>

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