RE: [oc] ATA-3 IP-Core

[Richard Herveille <richard@asics.ws>]

>Richard,
>Thanks for the info.  Any guess as to a timeframe for when OCIDEC-4 might be
>avail & the transfer speed supported?

There's currently no design effort for the OCIDEC-4 core. I am swamped with 
work right now. But it will become available. Because the cores use user 
programmable timings, it should support the fastest UDMA mode available at 
that time (currently UDMA-100). Which will be, in my humble opinion, the 
fastest transfer-rate for a long time. Because 100Mbytes per sec. is about 
the max. throughput for a standard PCI bus.

Richard


>Jim
>
>-----Original Message-----
>From: Richard Herveille [mailto:richard@asics.ws]
>Sent: Saturday, August 11, 2001 6:35 AM
>To: cores@opencores.org
>Subject: Re: [oc] ATA-3 IP-Core
>
>
>
>Hi Jim,
>
>The core is ATA/ATAPI-5 compliant. But it does not support UDMA. This would
>be the OCIDEC-4 core (which is still under revision). It does support
>single and multiword DMA transfers.
>
>Richard
>
> >Richard,
> >
> >Would you clarify for me the speed of the existing ATA Core's OCIDEC-3
> >Interface.
> >I'm not clear whether the core is ATA/ATAPI-3 or ATA/ATAPI-5 capable.
> >If we connect it to a new ATA-100 compatible HD, what is the data transfer
> >speed we can expect?
> >
> >Thanks,
> >Jim
> >
> >
> >
> >
> >Jim Kjendalen
> >Hardware Engineer
> >Adaptive Micro-Ware, Inc.
> >6917 Innovation Blvd.
> >Fort Wayne, IN  46818
> >Phone:  (219) 489-0046 ext. 270
> >Fax:  (219) 489-8087
> >jimkje@adaptivemicro.com
> >
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