Forgot to mention: I updated the spec as well .... on 3/19/01 20:25, Rudolf Usselmann at rudi@asics.ws wrote: > > I have finished the WISHBONE DMA/Bridge IP core and > checked in the Verilog Source code. > > Please see the "WISHBONE DMA" page for more info. > > http://www.opencores.org/cores/wb_dma > > Cheers ! Cheers ! -- rudi