Re: [oc] serial UART in cadence

[Eric Thompson <thompe2@rpi.edu>]

Frank Poppen wrote:

> "Oo.et.oO" wrote:
>
> > no one else around here really has experience in vhdl in cadence either.
>
> Hello Eric,
> I'm a little confused: As I know it (we usually use ModelSim or VSS
> but have Cadence, too) there is not ONE cadence Simulator. Do you want
> to use LEAPFROG VHDL simulator or Affirma NC VHDL simulator?
> For LEAPFROG: I tried to simulate the UART course with it and did not
> have any trouble.
> Best reagrds,
> Frank

i'm not sure which i want to use.  i'm just learning the cadence vhdl tools.
that is also why i'm having trouble.  i don't know where to start.  i do now.

i simulated a counter, multiplexer, etc.
i think the next thing i have to figure out is multiple file designs.
what are some differences between leapfrog (what i got familiar with today)
and affirma?
            thanks-
                eric

>
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