[oc] serial UART in cadence

[Eric Thompson <thompe2@rpi.edu>]

hi-
    I would like to try to do a simulation of the serial UART leading to
interfacing it with some other open cores for a class project on
core-based design.
    I do not have access to modelSim which i see the UART was originally
simulated with.  I do have access to cadence.  Does anyone know what it
would take to import this uart in cadence?  If i do "import vhdl" now it
complains that there is no std library.
is it named something different in cadence?  i have basic, analog, and a
bunch of others.
i'm rusty on vhdl so any help would be greatly appreciated.  thanks.
This project would also lead to at least my contributing to any cores we
use if possible.  The other students may also contribute as the project
moves ahead.
            thanks-
                eric thompson