Re: [oc] Modular FPGA Board: Block Diagram

[Wamnet@aol.com]

In a message dated 11/30/2000 2:04:03 AM Eastern Standard Time, 
Richard.Herveille@pie.nl writes:

> The trace length limit requires placing the FPGA close to the edge
>  connector. This implies placing the simm connector behind/above the FPGA.
>  Here is our next problem. The PCI bus is based on first reflective wave
>  switching (not incident wave). This means the signals is placed mid-level 
at
>  the bus(1.6V for 3.3V designs, 2.5V for 5V designs) and reflects at the end
>  of the line (in this case the simm-connectors). The reflection generates 
the
>  1.6->3.3V/ 2.5-5V step. This reflection has to traverse back and at some
>  point will reach the FPGA (but to late.)
>  
>  Correct me if I am wrong
>  
>  Richard Herveille


Nope - right on the money. We're a PCI SIG member (PCI ID 1660) and you're 
correct in how tight the spec for PCI is. 

Can't wait to see what Infiniband (new bus std) is like...