[oc] miniUART VHDL errors in XIlinx Foundation series

["radaR" <radarski@surfree.com>]

In the information on the miniUART core, it is claimed that it's been 
sucessfully used with the XIlinx Foundation Series 2.1i. However, 
serveral errors and warnings occur when attempting to simulate, or even 
just from running "Check Syntax". Among them are:

UART_lib.vhd:
	Warning: Initial values for signals are not supported for 
synthesis.

uarttest.vhd:
	Warning: Initial values for signals are not supported for 
synthesis.
	Error: "Time" is an unsupported type on line 0
	Error: This form of wait statement is not supported for synthesis 
on line 148. ("wait for 5 ns")

Can anyone offer any information on how these warnings/errors can be 
reconciled with the fact that it has worked successfully for the author?

As a minor issue, what is the rationale for putting the small UART_Def 
package in a file with a different name (uart_lib)?
	
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