[oc] multi_second.vhd

[Jimmy Hui <pinesystems@home.com>]

Hi,

I am quite new to vhdl.  I wrote a clock divider:

1.  Input - CLK in = 1.8432 Mhz
2.  Output - SECOND
3.  Output - 0.25 SECOND

Can someone comment if this is the optimal design?

Thanks,

Jimmy

multi_second.vhd