Re: [oc] Beyond Transmeta...

["Marko Mlinar" <Marko.Mlinar@campus.fri.uni-lj.si>]

> I have been doing a little programming. If you want to see what an 3bit
add
> network looks like you can download what I have done so far at...
>
> http://members.aol.com/suboner/binet.zip
>
> Its a windows executable (:p), but there is source code there and since it
> was written for gtk+ using glade, you can probably take that source code
and
> alter it (add bnet.c to the make file) to have it compile for Linux. It
> basicly shows a simple network, I gave the bits names so you can
understand
> them a little better, and the instruction 4 bit instruction is under that
> name along with a name for the instruction.
great. I will take a look at it - as you probably know are simulations very
neccessary...

> > suppose you know that your network can be only slower than normal add
> > network consisting only of gates. I think that 32b+32b adder needs 23
layers
> > of logic. For same implementation you would need much more gate layers!
>
> I'm not sure what a gate layer is, but I believe it would take 124
> instructions to comple a 32bit add, and 4 instructions can be executed in
> parallel (except the last 4), which result in 32 cycles, 32 layers that
can
> be done in parallel.
gate layer (I don't know if this is official name) = gates (like NAND) that
can be
executed in parallel and must wait for result from previous gate layer.

> > uhh... this thing has to be done in HW. It really complicates all thing.
> > it would be better if you would route things staticaly (by compiler),
and
> > then
> > use free instructions/functions (if not free =>wait). Only small
> > instructions
> > should be inlined.
> > BTW: you can pipeline one function (if it doesn't contain loops) so you
can
> > execute 1 function/cycle, regardless of function length.
>
> I'm a little lost here, as I am not sure which you are saying is
complicated,
> the perstent network or the processor network?
I think there is no difference and upper statement is valid for both.

> > You could also have two bits for each signal:
> > 1. data (same meaning)
> > 2. 'clock' bit - changes only when data hasn't changed
> > Using this principle network can be totally unsinchronized.
>
> I'm sorry, I think I am sleepy or something, I've been having a hard time
> following you here... I'll think about what you have said and reread it
> tomarrow, if you want to you can try explaining it diffrently, maybe its
just
> that I do not enough knowledge of hardware in some cases, and
> misunderstanding in others. Well I am off to bed, thanks, and don't forget
if
> you can check out my program above.
:) Ok, I will rephrase my idea:
suppose you have a NOT (gate or 1b proc.), then the following input would
result
outputs:
in    out
0    1
1    0
1    0
1    0
using my idea (2.) you get:
in    out    'clk'
0    1    1
1    0    0
1    0    1
1    0    0

I hope this makes things clear,
    Marko