回信： [oc] OpenRISC with "known" architectures.

[jimmy87@sunplus.com.tw]

I don't think it's a good idea to implement something like ARM's ISA.
If our ISA is ARM, then some companies would be sued by ARM if
they implement OR1(if OR1 is like ARM). Then it's hard to push
OR1K more popular. If not popular and not used extensively,
then our intention of free core would be useless!!!
So, I personally feel we should make a brand new ISA.
Best regards,
Jimmy






"ULF SAMUELSSON" <ulf.samuelsson@mbox308.swipnet.se> 於 2000/03/06 05:28:44 PM

請回應 給 cores@opencores.org

收件人：  cores@opencores.org
副本抄送： (副本密送： jimmy87/Sunplus)

主旨：    [oc] OpenRISC with "known" architectures.



I saw that you guys were threatened by ARM Ltd, if you tried to do an ARM
architecture.
FYI, at least some of their patents are on a very loose ground in my opinion.
Prior art, or simply not appliable.
For instance , their "patent" on the THUMB architecture relies on
a hardwired instruction set, which is by definition not applicable
on an FPGA implementation ,since you can always reload the FPGA with something
else.
Another way to go around the patent is to let the ARM mode execute 33 bit
instructions
and the thumb mode to execute 32 but instructions.
Third way is to have 2 extra bits on the databus for instruction fetch
which for every instruction determines if it is ARM or THUMB together with the

Extra Bit 0 = 0: use PSR.T to determine ARM or THUMB
Extra Bit 0 = 1: Use Extra bit 1 to determine ARM or THUMB decoding.
    The extra bits convert the multiple instruction set to become a single
instruction set
    Extra bit 0 can of course be hardwired (outside the core) to make the core
This can also be used with a decompressing instruction cache.
If you decompress the Thumb instructions into the cache, the core only needs to
execute the ARM instructions, making the part a single instruction set computer
actually invalidating most of their patents.
Decompressing Instruction caches were described alreay by a Professor Pattersson
in 1983.

The National Semiconductor HPC architecture in itself probably invalidates the
patent
since You can argue it already it implements the idea described in the patent.

Would be fun to see a free ARM implementation.

Best Regards,
Ulf Samuelsson
ulfs@dof.se