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Re: [oc] Open Core

To: <cores@opencores.org>
Subject: Re: [oc] Open Core
From: "Damjan Lampret" <lampret@opencores.org>
Date: Tue, 29 Feb 2000 23:54:50 +0100
Cc: "kash" <kash@ix.netcom.com>
Organization: OPENCORES.ORG
References: <000801bf82c3$424c6640$f90df00a@PROXIM>
Reply-To: cores@opencores.org
Sender: owner-cores@opencores.org


Entire OR1K with SDRAM controller fits XCV50 with BlockRAMs are used for
caches.

How much funds we would need for a std cell ASIC prototype (possibly for
.25u).

regards, Damjan

References:
- [oc] Open Core
  - From: "kash" <kash@ix.netcom.com>

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