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Re: [oc] Re: coding conventions
Hi,
>
>I've been lurking on this issue up to now, but I'm going to say my
piece -
>though it sounds like most of you won't go for it.
>
>Here's what I use:
> Port names begin with a Capital letter, and are generally kept as
short as
>possible.
>I can't stand the idea of a xxxxAAAAnnnnn naming convention. I hate
long
>names. They really make the code look ugly and provide very little
Hating or Loving Long Names is not the question here. The point of
consideration is how can we interpret every detail of a signal, just by
looking at its name. The module that generates the signal, nature of
signal, its function.....& so on.
>information that a few well placed comments can't provide. Give the
signal
Ofcourse comments are necessary. But these comments can't be replacement
for info-packed signal names.
>a moniker that is understandable, and follow it with a description
after the
>signal declaration:
> signal DCas : std_logic; -- Dram Column Address Strobe.
>
> Internal signal and variables begin with a lower case letter. If it
is a
>registered signal, I append it with a "_q". If it is a falling edge
clocked
>signal, it is appended with a "_qf". Negative logic signals are
appended
>with "_n". Tri-state signals are with "_z". Combinations of the
previous
>are often used. Types get an "_t".
> signal cas_qfn : std_logic; -- Falling edge clocked CAS*.
>
> As far as keeping track of what module a signal comes from, I just
make
>that
>clear as a comment after the port mapping in the component
instantiation:
> dram_m : drc
> port map (
> Adrs => Adrs; -- From adrs_mux
> DCas => DCas; -- To control
>
Think again, you may also start loving the proposed naming convention
when you are designing huge systems. I have experienced both ways, one
without this convention and once with it. These convention definitely
prove handy even when debugging the design.
Regards
Harish
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