Yes, you have come up with a few nice agreeable suggestion. First thing, about the header I fully agree with you. But since the revision list may keep growing I would like to put it at the end of the code. Ofcourse the header will be at the begining of the code, only the revision list becomes the footer. Am I right ? Also I agree with your suggestion on Architecture naming. I will be sending the updated "conventions" file. Regards Harish ---------Included Message---------- >Date: Sun, 13 Feb 2000 20:14:30 +0200 >From: "Ovi Lupas" <olupas@opencores.org> >Reply-To: <cores@opencores.org> >To: <cores@opencores.org> >Subject: Re: [oc] Coding Conventions are up > >>Architecture names should be entity names followed by 3 letter suffix "beh" for behavioural description, "rtl" for rtl >>description or "str" for structural description. > >This sounds a little redundant to me. The architecture usually is : >architecture ArchName of EntityName is > >So, the entity name always appears in the arch decl. I think more appropiate to name : > >architecture Behavioural of EntityName is >architecture Structural of EntityName is > >Of course, all this are from VHDL point of view... ;-) >In Verilog, I have no clue. > >regards, Ovidiu > > > ---------End of Included Message---------- _____________________________________________________________ Tired of limited space on Yahoo and Hotmail? Free 100 Meg email account available at http://www.dacafe.com
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>Architecture names should be
entity names followed by 3 letter suffix "beh" for behavioural
description, "rtl" for rtl
>description or "str" for structural description. This sounds a little redundant to me.
The architecture usually is :
architecture ArchName of EntityName is
So, the entity name always appears in the arch
decl. I think more appropiate to name :
architecture Behavioural of EntityName
is
architecture Structural of EntityName
is Of course, all this are from VHDL point of view...
;-)
In Verilog, I have no clue.
regards, Ovidiu
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