head	1.1;
branch	1.1.1;
access;
symbols
	arelease:1.1.1.1
	avendor:1.1.1;
locks; strict;
comment	@# @;


1.1
date	2005.04.23.00.40.55;	author tak.sugawara;	state Exp;
branches
	1.1.1.1;
next	;
commitid	1113426998c94567;

1.1.1.1
date	2005.04.23.00.40.55;	author tak.sugawara;	state Exp;
branches;
next	;
commitid	1113426998c94567;


desc
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1.1
log
@Initial revision
@
text
@# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = F:\yacc\syn\xilinx
SET speedgrade = -4
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
# SET outputdirectory = F:\yacc\syn\xilinx
SET device = xc3s200
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = ft256
SET createndf = False
SET designentry = VHDL
SET devicefamily = spartan3
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Synchronous_FIFO family Xilinx,_Inc. 5.0
# END Select
# BEGIN Parameters
CSET memory_type=Block_Memory
CSET write_acknowledge_flag=false
CSET data_width=8
CSET write_error_flag=false
CSET read_acknowledge_sense=Active_Low
CSET data_count_width=1
CSET fifo_depth=512
CSET component_name=fifo
CSET data_count=false
CSET read_acknowledge_flag=false
CSET read_error_sense=Active_Low
CSET read_error_flag=false
CSET write_acknowledge_sense=Active_Low
CSET write_error_sense=Active_Low
# END Parameters
GENERATE



@


1.1.1.1
log
@no message
@
text
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