head 1.2; access; symbols rel_00_01_alpha:1.1.1.1 start:1.1.1.1 avendor:1.1.1; locks; strict; comment @# @; 1.2 date 2004.12.18.14.37.28; author sfielding; state dead; branches; next 1.1; 1.1 date 2004.10.11.03.59.09; author sfielding; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2004.10.11.03.59.09; author sfielding; state Exp; branches; next ; desc @@ 1.2 log @Removed html documentation @ text @ speedCtrlMux.v 
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// speedCtrlMux.v                                               ////
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//>                           ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from <http://www.opencores.org/lgpl.shtml>                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Id: index.htm,v 1.1 2004/10/11 03:59:09 sfielding Exp $
//
// CVS Revision History
//
// $Log: index.htm,v $
// Revision 1.1  2004/10/11 03:59:09  sfielding
// Initial revision
//
//
module speedCtrlMux (directCtrlRate, directCtrlPol, sendPacketRate, sendPacketPol, sendPacketSel, fullSpeedRate, fullSpeedPol);
input   directCtrlRate;
input   directCtrlPol;
input   sendPacketRate;
input   sendPacketPol;
input   sendPacketSel;
output  fullSpeedRate;
output  fullSpeedPol;

wire   directCtrlRate;
wire   directCtrlPol;
wire   sendPacketRate;
wire   sendPacketPol;
wire   sendPacketSel;
reg   fullSpeedRate;
reg   fullSpeedPol;


always @@(directCtrlRate or directCtrlPol or sendPacketRate or sendPacketPol or sendPacketSel)
begin
  if (sendPacketSel == 1'b1) 
  begin
  fullSpeedRate <= sendPacketRate;
  fullSpeedPol <= sendPacketPol;
  end
  else
  begin
  fullSpeedRate <= directCtrlRate;
  fullSpeedPol <= directCtrlPol;
  end
end

endmodule
@ 1.1 log @Initial revision @ text @d53 1 a53 1 // $Id$ d57 4 a60 1 // $Log$ @ 1.1.1.1 log @Created @ text @@