head 1.13; access; symbols rel_1_1:1.13 rel_1_0:1.13 rel_0_6_1_beta:1.12 rel_0_6__beta:1.12 rel_0_6_beta:1.12 rel_0_5_beta:1.12 rel_0_4_beta:1.12 rel_0_3_beta:1.12 rel_0_2_beta:1.12 rel_0_1_beta:1.12; locks; strict; comment @# @; 1.13 date 2006.07.14.01.11.13; author arniml; state Exp; branches; next 1.12; commitid 5f0344b6ef2f4567; 1.12 date 2006.07.14.01.06.36; author arniml; state Exp; branches; next 1.11; commitid 5a3244b6ee1b4567; 1.11 date 2005.11.02.21.16.34; author arniml; state Exp; branches; next 1.10; commitid 7e1443692ca24567; 1.10 date 2005.09.13.21.27.12; author arniml; state Exp; branches; next 1.9; commitid 9bc4327442a4567; 1.9 date 2005.06.08.19.23.24; author arniml; state Exp; branches; next 1.8; commitid 5bec42a745aa4567; 1.8 date 2005.05.04.20.20.15; author arniml; state Exp; branches; next 1.7; commitid 2b4942792e794567; 1.7 date 2004.10.25.21.37.36; author arniml; state Exp; branches; next 1.6; 1.6 date 2004.10.24.09.13.06; author arniml; state Exp; branches; next 1.5; 1.5 date 2004.09.12.10.17.58; author arniml; state Exp; branches; next 1.4; 1.4 date 2004.06.30.21.25.54; author arniml; state Exp; branches; next 1.3; 1.3 date 2004.06.29.20.41.52; author arniml; state Exp; branches; next 1.2; 1.2 date 2004.05.20.22.00.59; author arniml; state Exp; branches; next 1.1; 1.1 date 2004.05.18.12.07.22; author arniml; state Exp; branches; next ; desc @@ 1.13 log @name tag added @ text @ Known bugs of the T48 uController core ====================================== Version: $Date: 2006/07/14 01:06:36 $ $Name$ Release 0.6.1 BETA ------------------ ******************************************************************************* Deassertion of PROG too early PROG is deasserted in XTAL2 cycle which might lead to read data being already invalid (tri-stated) when the core samples P2[3:0] at the end of XTAL3. Fixed in: clock_ctrl.vhd 1.12 Fix will be included in next release. Release 0.6 BETA ---------------- ******************************************************************************* Deassertion of PROG too early See above. ******************************************************************************* P2 Port value restored after expander access After access to expander interface (ANLD Pp; MOVD A,Pp; MOVD Pp,A; ORLD Pp) the port value of P2 is restored. This is wrong according to chapter "Port 2 Operations" of the "Expanded MCS-48 System" manual. It states that previously latched I/O information will be removed and not restored. Fixed in: p2.vhd 1.8 Fix will be included in next release. ******************************************************************************* Problem when INT and JMP When code is executed from Memory Bank 1, the injected CALL triggered by the interrupt does not always vector to address 3. This happens because of a bus collision between the decoder unit and the db_bus unit. The resulting address can be either: * 000h, 001h, 002h, 003h for external and timer interrupt * 004h, 005h, 006h, 007h for timer interrupt The problem was introduced in release 0.6 BETA when the glitch on PCH was fixed. Fixed in: decoder.vhd 1.21 New regression test: int_on_mb1 Fix will be included in next release. Release 0.5 BETA ---------------- ******************************************************************************* Deassertion of PROG too early See above. ******************************************************************************* P2 Port value restored after expander access See above. ******************************************************************************* Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt An interrupt occuring during the execution of a JMP instruction, forces bit 11 of the target address to 0. This corrupts target addresses that are located in Program Memory Bank 1. Fixed in: int.vhd 1.5 New regression test: white_box/int_on_int Fix will be included in next release. ******************************************************************************* MSB of Program Counter changed upon PC increment The current implementation of the Program Counter allows that the MSB (bit 11) is modifed when the PC increments at address 07FFh linear code execution. This is contrary to the description found in "The Expanded MCS-48 System" which states that bit 11 is only altered by JMP and CALL/RET but not by normal increment. Fixed in: pmem_crtl.vhd 1.4 New regression test: white_box/pc_wrap_bit11 Fix will be included in next release. ******************************************************************************* Wrong clock applied to T0 After executing the 'ENT0 CLK' instruction, the internal clock (XTAL divided by 3) should be applied to T0. The t48_core applies clk_i to T0. This is equal to XTAL in the current implementation of t8048 and others. Therefore, the clock at T0 is three times faster than specified. Fixed in: clock_ctrl.vhd 1.7 t48_core.vhd 1.8 Fix will be included in next release. Release 0.4 BETA ---------------- ******************************************************************************* P2 Port value restored after expander access See above. ******************************************************************************* Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt See above. ******************************************************************************* MSB of Program Counter changed upon PC increment See above. ******************************************************************************* Wrong clock applied to T0 See above. ******************************************************************************* RD' and WR' not asserted for INS A, BUS and OUTL BUS, A The control signals RD' and WR' are not asserted when the instructions INS A, BUS and OUTL BUS, A are executed. The BUS is read or written but the control signals are missing. Fixed in: decoder.vhd 1.16 Fix will be included in next release. ******************************************************************************* P1 constantly in push-pull mode in t8048 Port P1 is constantly driven by an active push-pull driver instead of an open-collector driver type. This inhibits using any bit of P1 in input direction. Fixed in: t8048.vhd 1.4 Fix will be included in next release. Release 0.3 BETA ---------------- ******************************************************************************* P2 Port value restored after expander access See above. ******************************************************************************* Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt See above. ******************************************************************************* MSB of Program Counter changed upon PC increment See above. ******************************************************************************* Wrong clock applied to T0 See above. ******************************************************************************* RD' and WR' not asserted for INS A, BUS and OUTL BUS, A See above. ******************************************************************************* P1 constantly in push-pull mode in t8048 See above. ******************************************************************************* PSENn Timing PSENn is erroneously activated during read or write from external memory when the read and write strobe signals RDn and WRn are active. This happens when code is executed from external Program Memory. The problem lies in the decoder module where the PSENn signal is generated based on the current machine cycle. Fixed in decoder.vhd 1.15 Added waveform check for PSENn in if_timing.vhd 1.3 New regression test: white_box/psen_rd_wr_timing Fix will be included in next release. Release 0.2 BETA ---------------- ******************************************************************************* P2 Port value restored after expander access See above. ******************************************************************************* MSB of Program Counter changed upon PC increment See above. ******************************************************************************* Wrong clock applied to T0 See above. ******************************************************************************* RD' and WR' not asserted for INS A, BUS and OUTL BUS, A See above. ******************************************************************************* P1 constantly in push-pull mode in t8048 See above. ******************************************************************************* PSENn Timing See above. ******************************************************************************* Program Memory bank can be switched during interrupt During an interrupt service routine (i.e. after vectoring to location 3 or 7 of the Program Memory and befor executing the RETR instruction) the Program Memory bank can be switched by executing a JMP or CALL instruction. These instructions honour the current state of the Program Memory Bank Flag and thus switch the Program Memory bank upon execution. Fixed in: int.vhd 1.2 decoder.vhd 1.14 Updated regression test: black_box/mb/int Fix will be included in next release. Release 0.1 BETA ---------------- ******************************************************************************* P2 Port value restored after expander access See above. ******************************************************************************* MSB of Program Counter changed upon PC increment See above. ******************************************************************************* Wrong clock applied to T0 See above. ******************************************************************************* RD' and WR' not asserted for INS A, BUS and OUTL BUS, A See above. ******************************************************************************* PSENn Timing See above. ******************************************************************************* Program Memory bank can be switched during interrupt See above. ****************************************************************************** External Program Memory ignored when EA = 0 The external Program Memory is always ignored when EA = 0 with the t8048 system toplevel. Desired behaviour is to access external Program Memory when code has to be fetched from an address location that is outside the internal Program Memory. Fixed in t8048.vhd 1.3 Fix will be included in next release. ****************************************************************************** ANL and ORL to P2 read port status instead of port output register The ANL and ORL instructions for P2 read the port status and apply the logical operation on this value. Instead, they should read the port output register and operate on this value. Fixed in p2.vhd 1.5 Regression test: white_box/p2_port_reg_conflict Fix will be included in next release. ****************************************************************************** Counter is not incremented When in counter mode, the timer/counter module does not increment upon a falling edge of T1. Reason is a typo in the code for the edge detection signal t1_inc_s - it will never become true. Fixed in timer.vhd 1.3 Regression tests: black_box/cnt/cnt black_box/cnt/int Fix will be included in next release. @ 1.12 log @add bug report "Deassertion of PROG too early" @ text @d4 2 a5 1 Version: $Date: 2005/11/02 21:16:34 $ @ 1.11 log @add bug reports "Problem when INT and JMP" "P2 Port value restored after expander access" @ text @d4 16 a19 1 Version: $Date: 2005/09/13 21:27:12 $ d26 5 d66 5 @ 1.10 log @add bug report "Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt" @ text @d4 36 a39 1 Version: $Date: 2005/06/08 19:23:24 $ d46 5 d96 5 d143 5 d193 5 d244 5 @ 1.9 log @add bug report "MSB of Program Counter changed upon PC increment" @ text @d4 1 a4 1 Version: $Date: 2005/05/04 20:20:15 $ d11 12 d56 5 d98 5 @ 1.8 log @add bug Wrong clock applied to T0 @ text @d4 1 a4 1 Version: $Date: 2004/10/25 21:37:36 $ d11 14 d44 5 d81 5 d121 5 d167 5 @ 1.7 log @add bug RD' and WR' not asserted for INS A, BUS and OUTL BUS, A @ text @d4 20 a23 1 Version: $Date: 2004/10/24 09:13:06 $ d30 5 a44 1 d62 5 d97 5 d138 5 @ 1.6 log @add bug P1 constantly in push-pull mode in t8048 @ text @d4 1 a4 1 Version: $Date: 2004/09/12 10:17:58 $ d11 12 d39 5 d69 5 d105 5 @ 1.5 log @add bug PSENn Timing @ text @d4 17 a20 1 Version: $Date: 2004/06/30 21:25:54 $ d27 5 d52 5 @ 1.4 log @update bug description for Program Memory bank can be switched during interrupt @ text @d4 21 a24 1 Version: $Date: 2004/06/29 20:41:52 $ d31 5 d57 5 @ 1.3 log @add bug Program Memory bank can be switched during interrupt @ text @d4 1 a4 1 Version: $Date: 2004/05/20 22:00:59 $ d19 7 @ 1.2 log @add new bug for release 0.1 BETA @ text @d4 15 a18 1 Version: $Date:$ d24 5 @ 1.1 log @initial check-in describe bugs of release 0.1 BETA @ text @d4 1 a4 1 Version: $Id:$ d9 11 @