head 1.1; branch 1.1.1; access ; symbols INITIAL:1.1.1.1 ARIF_E_NUGROHO:1.1.1; locks ; strict; comment @# @; 1.1 date 2005.11.15.01.51.25; author arif_endro; state Exp; branches 1.1.1.1; next ; commitid 17d043793f114567; 1.1.1.1 date 2005.11.15.01.51.25; author arif_endro; state Exp; branches ; next ; commitid 17d043793f114567; desc @@ 1.1 log @Initial revision @ text @# $Id: README,v 1.1.1.1 2005/11/04 03:19:05 arif_endro Exp $ Directory Layout . |-- bench -> the test bench directory | |-- data -> data files, e.g. senddata.txt, rxin100DB.txt, start.txt | |-- doc -> documentation files | `-- source -> the VHDL source of this project. Test Bench If you want to run the test bench, then go to the bench subdirectory and then run the modelsim do file, i.e. `modelsim_bench.do'. This simulation will generate an output into a file called `send_out.txt', then you can compare this file with the original informations, i.e. `senddata.txt', but first you must discard the first 12 lines before starting the comparation. This comparation can be done automatically by running script `analyze.sh' on the bench subdirectory. Sincerely, Arif E. Nugroho @ 1.1.1.1 log @Initial Checkin. @ text @@