head	1.2;
access;
symbols;
locks; strict;
comment	@# @;


1.2
date	2002.09.01.14.20.26;	author jesus;	state Exp;
branches;
next	1.1;

1.1
date	2002.05.21.01.45.11;	author jesus;	state Exp;
branches;
next	;


desc
@@


1.2
log
@no message
@
text
@set process "5"
set part "2s200pq208"
set tristate_map "FALSE"
set opt_auto_mode "TRUE"
set opt_best_result "29223.458000"
set dont_lock_lcells "auto"
set input2output "20.000000"
set input2register "20.000000"
set register2output "20.000000"
set register2register "20.000000"
set wire_table "xis215-5_avg"
set encoding "auto"
set edifin_ground_port_names "GND"
set edifin_power_port_names "VCC"
set edif_array_range_extraction_style "%s\[%d:%d\]"

set_xilinx_eqn

load_library xis2

read -technology xis2 {
../../../rtl/vhdl/PPX_Pack.vhd
../../../rtl/vhdl/PPX_ALU.vhd
../../../rtl/vhdl/PPX_Ctrl.vhd
../../../rtl/vhdl/PPX_PCS.vhd
../../../rtl/vhdl/PPX16.vhd
../../../rtl/vhdl/PPX_RAM.vhd
../../../rtl/vhdl/PPX_Port.vhd
../../../rtl/vhdl/PPX_TMR.vhd
../src/ROM55_Test_leo.vhd
../../../rtl/vhdl/P16C55.vhd
}

pre_optimize

optimize -hierarchy=auto -delay -pass 1 -pass 2 -pass 3 -pass 4

optimize_timing

report_area

report_delay

write p16c55_leo.edf
@


1.1
log
@First commit
@
text
@d22 10
a31 9
../../../rtl/vhdl/AX_Pack.vhd
../../../rtl/vhdl/AX_Reg.vhd
../../../rtl/vhdl/AX_ALU.vhd
../../../rtl/vhdl/AX_PCS.vhd
../../../rtl/vhdl/AX8.vhd
../../../rtl/vhdl/AX_Port.vhd
../../../rtl/vhdl/AX_TC8.vhd
../src/ROM1200_Echo_leo.vhd
../../../rtl/vhdl/A90S1200.vhd
d36 1
a36 1
optimize -hierarchy=auto
d44 1
a44 1
write a90s1200.edf
@