head 1.7;
access;
symbols
initial_import:1.1.1.1 pci_blue_interface:1.1.1;
locks; strict;
comment @# @;
1.7
date 2001.09.26.09.48.40; author bbeaver; state Exp;
branches;
next 1.6;
1.6
date 2001.06.25.08.49.35; author bbeaver; state Exp;
branches;
next 1.5;
1.5
date 2001.06.20.11.24.58; author bbeaver; state Exp;
branches;
next 1.4;
1.4
date 2001.06.13.11.58.41; author bbeaver; state Exp;
branches;
next 1.3;
1.3
date 2001.06.08.08.40.35; author bbeaver; state Exp;
branches;
next 1.2;
1.2
date 2001.02.26.11.50.06; author bbeaver; state Exp;
branches;
next 1.1;
1.1
date 2001.02.21.15.27.28; author bbeaver; state Exp;
branches
1.1.1.1;
next ;
1.1.1.1
date 2001.02.21.15.27.28; author bbeaver; state Exp;
branches;
next ;
desc
@@
1.7
log
@Starting to stub in the Target State Machine.
Doesn't compile yet. Sorry.
@
text
@
pci_test_system\pci_test_top.v
pci_example_chip\pci_example_chip.v
pci_blue_arbiter\pci_blue_arbiter.v
pci_blue_interface\pci_blue_interface.v
pci_blue_master\pci_blue_master.v
pci_blue_target\pci_blue_target.v
pci_blue_target\pci_blue_config_regs.v
pci_blue_fifos\pci_blue_fifo_flags.v
pci_blue_fifos\pci_blue_fifos.v
pci_example_chip\pci_clk_reset_pads.v
pci_example_chip\pci_target_pads.v
pci_example_chip\pci_master_pads.v
pci_vendor_lib\pci_vendor_lib.v
pci_example_chip\pci_example_host_controller.v
pci_test_system\pci_test_commander.v
pci_bus_monitor\pci_bus_monitor.v
pci_behaviorial_device\pci_behaviorial_device.v
pci_behaviorial_device\pci_behaviorial_master.v
pci_behaviorial_device\pci_behaviorial_target.v
pci_example_chip\monitor_pci_interface_host_port.v
Readme
reminders.v
..\misc\synchronizer_flop.v
..\..\SYNAPTICAD.7.9F
..\..\SYNAPTICAD.7.4
..\..\SYNAPTICAD
..\..\VLOGGER
pci_blue_include
..\..\SYNAPTICAD.7.9F\lib\verilog
..\..\SYNAPTICAD.7.4\lib\verilog
..\..\SYNAPTICAD\lib\verilog
..\..\VLOGGER\lib\verilog
.v
.vo
.vh
VerboseSamples
VerboseSequenceVerification
VerboseDelays
VerboseFileInput
SampleIf
SampleThen
SampleElse
SignalDirection
GenerateSampleHdlCode
GenerateMarkerHdlCode
GenerateDelayHdlCode
ExecuteFromTopLevel
CycleClock
CycleClockEdge
VerilogTimeOutLength
VhdlTimeOutLength
SystemCTimeOutLength
VeraTimeOutLength
VerilogIncludeDelayTime
VhdlIncludeDelayTime
SystemCIncludeDelayTime
VeraIncludeDelayTime
VerilogSignalType
VhdlSignalType
SystemCSignalType
VhdlGenerateAbortCode
SystemCGenerateAbortCode
@
1.6
log
@working on master. No real progress
@
text
@d3 1
a3 1
d26 2
a27 1
d29 6
a34 5
C:\SYNAPTICAD.7.4\
C:\SYNAPTICAD\
C:\VLOGGER\
pci_blue_include\
C:\free_ip\pci_blue_interface\
d37 4
a40 3
C:\SYNAPTICAD.7.4\lib\verilog\
C:\SYNAPTICAD\lib\verilog\
C:\VLOGGER\lib\verilog\
a46 3
@
1.5
log
@Working on Synthesizable PCI Master
@
text
@d15 1
a25 3
pci_blue_include\pci_blue_options.vh
pci_blue_include\pci_blue_constants.vh
untitled0Tim.v
@
1.4
log
@Stubbing in the PCI Config Registers
@
text
@a15 1
Readme
a17 1
reminders.v
d23 2
@
1.3
log
@Working on pci_blue_master
Adding state machine and carefully crafted
FRAME and IRDY next value function
This code compiles, but does not function at all
The previous version should be used when exploring
the test framework.
@
text
@d5 11
a16 1
pci_blue_interface\pci_blue_interface.v
a20 4
pci_vendor_lib\pci_vendor_lib.v
pci_example_chip\pci_example_chip.v
pci_example_chip\pci_target_pads.v
pci_example_chip\pci_clk_reset_pads.v
a24 5
pci_blue_arbiter\pci_blue_arbiter.v
pci_blue_fifos\pci_blue_fifos.v
pci_blue_fifos\pci_blue_fifo_flags.v
pci_blue_master\pci_blue_master.v
pci_blue_target\pci_blue_target.v
@
1.2
log
@working on the example host interface
@
text
@d2 26
a27 1
d29 1
a34 24
pci_test_system\pci_test_top.v
Readme
pci_blue_include\pci_blue_constants.vh
pci_blue_include\pci_blue_options.vh
pci_blue_interface\pci_blue_interface.v
pci_example_chip\pci_example_host_controller.v
pci_test_system\pci_test_commander.v
reminders.v
pci_bus_monitor\pci_bus_monitor.v
pci_vendor_lib\pci_vendor_lib.v
pci_example_chip\pci_example_chip.v
pci_example_chip\pci_target_pads.v
pci_example_chip\pci_clk_reset_pads.v
pci_behaviorial_device\pci_behaviorial_device.v
pci_behaviorial_device\pci_behaviorial_master.v
pci_behaviorial_device\pci_behaviorial_target.v
pci_example_chip\monitor_pci_interface_host_port.v
pci_blue_arbiter\pci_blue_arbiter.v
pci_blue_fifos\pci_blue_fifos.v
pci_blue_fifos\pci_blue_fifo_flags.v
pci_blue_master\pci_blue_master.v
pci_blue_target\pci_blue_target.v
d36 1
d45 32
@
1.1
log
@Initial revision
@
text
@d14 1
a27 1
pci_blue_interface\pci_blue_interface.v
@
1.1.1.1
log
@Initial Import of pci_blue_interface
Only the behaviorial code works
There is no synthesizable code in this initial source import
@
text
@@