head 1.1; branch 1.1.1; access ; symbols noReleaseTag:1.1.1.1 noVendorName:1.1.1; locks ; strict; comment @# @; 1.1 date 2003.02.10.04.04.39; author doru; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2003.02.10.04.04.39; author doru; state Exp; branches ; next ; desc @@ 1.1 log @Initial revision @ text @ Sources Main Page Modules Related Pages

Sources

Sources

The source package contains the following files, in the compiling order:

std_util.vhd
- Type conversion routines ofted used throughout the other source files in this project
- Basic arithmetic functions
- Sign and zero-extend functions
- Vector comparision function
pavr_util.vhd
- Bypass Unit access function
- Interrupt arbitrer function
pavr_constants.vhd
- Constants needed by pAVR
- When costumizing pAVR, look and modify (seek-and-destroy) here.
pavr_data_mem.vhd
pavr_alu.vhd
pavr_register_file.vhd
pavr_io_file.vhd
pavr_control.vhd
- pAVR pipeline (pAVR kernel)

Test sources

The test sources in this package implement all the tests presented above.
The test source package contains the following files:

test_pavr_alu.vhd
Tests the ALU.
test_pavr_control_interrupts.vhd
This test is yet to be done.
test_std_util.vhd
Tests the utilities defined in `std_util.vhd'.
test_pavr_data_mem.vhd
Tests the Data Memory.
test_pavr_register_file.vhd
Tests the Register File.
test_pavr_io_file.vhd
Tests the IO File.
test_pavr_constants.vhd
Defines constants needed by the main test entity.
test_pavr_util.vhd
Defines utilities needed by the main test entity.
test_pavr_pm.vhd
Defines the Program Memory that is needed by the main test entity.
test_pavr.vhd
Defines the main test entity.
Tests pAVR as a whole.

Conventions used when writting the VHDL sources

The terminology used reflects the data flow.
For example, `pavr_s4_s6_rfwr_addr1' is assigned in s3 (by the instruction decoder), shifts into `pavr_s5_s6_rfwr_addr1', that finally shifts into `pavr_s6_rfwr_addr1' (terminal register). Only this one carries information actually used by hardware resource managers. This particualr one signalizes an access request to the Register File write port manager.

Process splitting strategy:

requests to hardware resources are managed by dedicated processes, one VHDL process per hardware resource.
a main asynchronous process (instruction decoder) computes values that initialize the pipeline in s3.
a main synchronous process assings new values to pipeline registers.

Todo:: Replace `next_...' signals family with a (pretty wide) state decoder.

Licensing: Please read the licensing terms.

Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by

1.2.16

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