head 1.1; branch 1.1.1; access ; symbols noReleaseTag:1.1.1.1 noVendorName:1.1.1; locks ; strict; comment @# @; 1.1 date 2003.02.10.04.04.51; author doru; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2003.02.10.04.04.51; author doru; state Exp; branches ; next ; desc @@ 1.1 log @Initial revision @ text @ ALU
Main Page   Modules   Related Pages  

ALU
[Pipeline details]

ALU description
The ALU is not a potentially conflicting resource, as it is fully controlled by pipeline stage s5.

There are two ALU operands. The first operand is taken either from RF read port 1, if it's an 8 bit operand, or taken from RF read port 1 (lower 8 bits) and from RF read port 2 (higher 8 bits), if it's a 16 bit operand. The second operand is taken either from the RF read port 2 or directly from the instruction opcode; it is always 8 bit-wide.
Both operands are fed to the ALU through the Bypass Unit.
All ALU-requiring instructions write their result into the Bypass Unit.
Details about the ALU hardware resource (connectivity, ALU opcodes) can be found here.
Instructions that make use of the ALU-related pipeline registers:
Plugging the ALU into the pipeline
The pipeline registers related to ALU access are presented in the picture below.
From this picture, it can also easely figured out instructions' timing.

pavr_pipe_alu_01.gif

Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by doxygen1.2.16
@ 1.1.1.1 log @Importing into repository the new directory structure. @ text @@