head 1.1; branch 1.1.1; access ; symbols noReleaseTag:1.1.1.1 noVendorName:1.1.1; locks ; strict; comment @# @; 1.1 date 2003.02.10.04.05.18; author doru; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2003.02.10.04.05.18; author doru; state Exp; branches ; next ; desc @@ 1.1 log @Initial revision @ text @ SREG port Main Page Modules Related Pages

SREG port
[IO File]

SREG port connectivity

Requests to this port

pavr_s5_alu_sregwr_rq
This signalizes that an instruction that uses the ALU wants to update the arithmetic flags.
Flags I (general interrupt enable, SREG(7)) and T (transfer bit, SREG(6)) are left unchanged.
pavr_s5_setiflag_sregwr_rq
This sets the I flag.
Only RETI instruction needs this.
pavr_s5_clriflag_sregwr_rq
This clears the I flag.
No instruction explicitely requests this.
This is only requested when an interrupt is acknowledged (during the consequent implicit CALL).

Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by

1.2.16

@ 1.1.1.1 log @Importing into repository the new directory structure. @ text @@

SREG port [IO File]

SREG port
[IO File]