head 1.1; branch 1.1.1; access ; symbols INITIAL:1.1.1.1 ARIF_E_NUGROHO:1.1.1; locks ; strict; comment @# @; 1.1 date 2005.12.06.02.47.45; author arif_endro; state Exp; branches 1.1.1.1; next ; commitid 4fe74394fbb84567; 1.1.1.1 date 2005.12.06.02.47.45; author arif_endro; state Exp; branches ; next ; commitid 4fe74394fbb84567; desc @@ 1.1 log @Initial revision @ text @# $Id: README,v 1.2 2005/12/05 23:59:02 arif_endro Exp $ Directory Layout . |-- bench -> the test bench directory | |-- data -> data files, `ecb_tbl.txt' file used for verification. | |-- doc -> documentation files | `-- source -> the VHDL source of this project. Test Bench If you want to run the test bench, then go to the bench subdirectory and then run the modelsim do file, i.e. `modelsim_bench.do'. This simulation will generate an output into a file called `ecb_tbl_result_enc.txt' and `ecb_tbl_result_dec.txt', then you can analyze those file to see the result. Sincerely, Arif E. Nugroho @ 1.1.1.1 log @Initial Checkin. @ text @@