head 1.1; branch 1.1.1; access ; symbols arelease:1.1.1.1 avendor:1.1.1; locks ; strict; comment @# @; 1.1 date 2004.05.09.00.32.01; author bretthoward; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2004.05.09.00.32.01; author bretthoward; state Exp; branches ; next ; desc @@ 1.1 log @Initial revision @ text @library ieee; use ieee.std_logic_1164.all; entity clk_divider is port ( clk : IN std_logic; oneus_plus : INOUT std_logic ); end entity; architecture structural of clk_divider is signal counter : integer range 0 to 16; begin process ( clk ) begin if rising_edge(clk) then counter <= counter + 1; if (counter mod 16) = 0 then oneus_plus <= not oneus_plus; end if; end if; end process; end architecture; PACKAGE TIMER_PKG IS COMPONENT clk_divider END COMPONENT; END TIMER_PKG;@ 1.1.1.1 log @no message @ text @@