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1.1
date	2006.11.01.19.56.19;	author samiam95124;	state Exp;
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	1.1.1.1;
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1.1.1.1
date	2006.11.01.19.56.19;	author samiam95124;	state Exp;
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1.1.1.2
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1.1.1.3
date	2006.11.19.04.23.42;	author samiam95124;	state Exp;
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desc
@@


1.1
log
@Initial revision
@
text
@version 3
C:/Xilinx/ISEexamples/cpu8080/testbench.v
testbench
VERILOG
VERILOG
cpu8080_tbw.xwv
Clocked
-
-
100000000000
ns
GSR:true
PRLD:false
100000000
CLOCK_LIST_BEGIN
clock
20000000
20000000
10000000
10000000
100000000
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
addr
clock
b
clock
data
clock
g
clock
hsync_n
clock
inta
clock
intr
clock
r
clock
readio
clock
readmem
clock
reset
clock
reset_n
clock
vsync_n
clock
waitr
clock
writeio
clock
writemem
clock
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
addr_DIFF
b_DIFF
g_DIFF
hsync_n_DIFF
inta_DIFF
intr_DIFF
r_DIFF
readio_DIFF
readmem_DIFF
vsync_n_DIFF
writeio_DIFF
writemem_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clock
reset_n
waitr
hsync_n
inta
intr
readio
readmem
vsync_n
writeio
writemem
addr
b
g
r
data
SIGNAL_ORDER_END
-X-X-X-

@


1.1.1.1
log
@8080 CPU project
@
text
@@


1.1.1.2
log
@8080 CPU project
@
text
@a38 4
ps2_clk
clock
ps2_data
clock
d80 1
d85 1
a88 1
data
d92 1
a92 4
hsync_n
vsync_n
ps2_clk
ps2_data
@


1.1.1.3
log
@8080 CPU project
@
text
@d10 1
a10 1
200000000000
a30 2
diag
clock
a64 1
diag_DIFF
a72 1
waitr_DIFF
a98 1
diag
@