| CPU8080 Project Status | |||
| Project File: | cpu8080.ise | Current State: | Placed and Routed |
| Module Name: | cpu8080 |
|
No Errors |
| Target Device: | xc3s200-5pq208 |
|
No Warnings |
| Product Version: | ISE 8.2.02i |
|
Wed Sep 20 23:36:49 2006 |
| CPU8080 Partition Summary | |||
| No partition information was found. |
| Device Utilization Summary | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Flip Flops | 269 | 1,536 | 17% | |
| Number of 4 input LUTs | 1,084 | 1,536 | 70% | |
| Logic Distribution | ||||
| Number of occupied Slices | 641 | 768 | 83% | |
| Number of Slices containing only related logic | 641 | 641 | 100% | |
| Number of Slices containing unrelated logic | 0 | 641 | 0% | |
| Total Number 4 input LUTs | 1,191 | 1,536 | 77% | |
| Number used as logic | 1,084 | |||
| Number used as a route-thru | 107 | |||
| Number of bonded IOBs | 32 | 124 | 25% | |
| IOB Flip Flops | 1 | |||
| Number of GCLKs | 1 | 8 | 12% | |
| Total equivalent gate count for design | 10,256 | |||
| Additional JTAG gate count for IOBs | 1,536 | |||
| Performance Summary | |||
| Final Timing Score: | 0 | Pinout Data: | Pinout Report |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
| Timing Constraints: | All Constraints Met | ||
| Detailed Reports | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos |
| Synthesis Report | |||||
| Translation Report | Current | Fri Sep 15 23:58:22 2006 | 0 | 0 | 0 |
| Map Report | Current | Fri Sep 15 23:58:32 2006 | 0 | 0 | 3 Infos (0 filtered) |
| Place and Route Report | Current | Sat Sep 16 00:01:08 2006 | 0 | 0 | 2 Infos (0 filtered) |
| Static Timing Report | Current | Sat Sep 16 00:01:14 2006 | 0 | 0 | 2 Infos (0 filtered) |
| Bitgen Report | |||||
| Secondary Reports | ||
| Report Name | Status | Generated |
| Xplorer Report | ||