head 1.1; branch 1.1.1; access ; symbols arelease:1.1.1.1 avendor:1.1.1; locks ; strict; comment @# @; 1.1 date 2008.04.08.19.58.29; author fpga_is_funny; state Exp; branches 1.1.1.1; next ; commitid 2b3f47fbcb9e4567; 1.1.1.1 date 2008.04.08.19.58.29; author fpga_is_funny; state Exp; branches ; next ; commitid 2b3f47fbcb9e4567; desc @@ 1.1 log @Initial revision @ text @- Finish working for Specification of cpu6502_tc - Create high level testbench in assembler and hardware for testing all Op Codes (include accurate cycle timing) - Create simulation files for Modelsim - Create a simple .wlf file to demonstrate the cpu6502_tc - Update the HDL Designer files for better viewing and understanding@ 1.1.1.1 log @First Revision After the successfully functional test with a SoC of an APPLE][+, I corrected the wrong CVS log entry "$log$" to "$Log$" into all VHDL files. I hope this will not have a bad impact for cpu6502_tc...smile The CVS history in the VHDL files is fine now. @ text @@