head 1.4; access; symbols; locks; strict; comment @# @; 1.4 date 2001.09.03.13.18.30; author bbeaver; state Exp; branches; next 1.3; 1.3 date 2001.09.03.12.46.51; author bbeaver; state Exp; branches; next 1.2; 1.2 date 2001.09.03.12.16.35; author bbeaver; state Exp; branches; next 1.1; 1.1 date 2001.09.03.11.26.43; author bbeaver; state Exp; branches; next ; desc @@ 1.4 log @no message @ text @// This directory contains files which are too small to be projects in themselves. // // Examples of such files might be: // prototype copyright files // parameterizable cell libraries // files which implement some interesting low-level function // files which are used as components in several projects // // Each file should be self-documenting so that a quick glance would serve // to explain what it is and why it is here. // // As a courtesy, each file could also have a small entry here to make it // easy to browse the directory looking for interesting stuff. // // "opencores_copyright.v" is an example of a copyright file one might // include to control the use and abuse of a file stored in this web site. // // "synchronizer_flop.v" is a behaviorial description of a 1-bit flop. // It should be manually instantiated in EACH AND EVERY MODULE which // uses a flop to synchronize a signal from one clock domain to another. // In real use, the user of this file will generate a simulation module // which will behave like a normal flop when presented with 1, 0, X, or Z. // This special-purpose module will NOT have setup and hold tests. It will // NOT convert a valid value into an X due to setup timing being violated. // This module makes it possible to simulate gate-level netlists with // multiple clock domains without fear of making inappropriate X's. // // "grey_to_binary.v" is an example of code which takes a binary number // and converts it to grey code, and vice versa. // This module has a parameter which describes how wide the operands // are. // This module does not use for-loops to generate the functions. Instead, // it manually does the translation for widths up to 16 bits. // If the user wants fewer bits, the synthesis tool removes the extra. // // "plesiochronous_fifo.v" is an example of a FIFO which transfers packets // between two clock domains. // The clocks are REQUIRED to be close to one-another in frequency. // The Writer is REQUIRED to skip writes every so often, to make sure that // the FIFO doesn't overflow. // This file instantiates the synchronizer_flop mentioned above. // // "hamming_ecc_64.v" is an example of how to use 8 bits of redundant data to // correct single-bit errors and detect double-bit errors in 64 bits of data. // There are probably better ways to reorder the terms to reduce loads, and // to change the formulas to detect a larger percentage of likely errors. // @ 1.3 log @no message @ text @d43 5 @ 1.2 log @no message @ text @d36 8 @ 1.1 log @no message @ text @d15 3 d27 8 @