WisboneTK

WishboneTK output register

Description

WishboneTK output register is a parametrized output register with read-back support. It is 100% Wishbone compatible with the WishboneTK extensions. The bus-width and the output width can be configured separately. Output width can be larger than the bus size. In that case address signals should be used access various parts of the however the bus width is required to be bigger than the output width.

Wishbone datasheet

DescriptionSpecification
General Description Output register with readback support.
Supported cycles Slave read/write
Slave block read/write
Slave rmw
Data port size variable
Data port granularity 8 bits
Data port maximum operand size same as bus size
Data transfer ordering n/a
Data transfer sequencing n/a
Supported signal list and cross reference to equivalent Wishbone signals
Signal nameWishbone equiv.
CLK_I CLK_I
RST_I RST_I
CYC_I CYC_I
STB_I STB_I
WE_I WE_I
ACK_O ACK_O
SEL_I(..) SEL_I()
ADR_I(..) ADR_I()
DAT_I() DAT_I()
DAT_O() DAT_O()

Parameter description

Parameter nameDescription
widthNumber of bits in the output register
bus_widthSize of the data-bus
offsetBit-offset from where the output bits start within the data

Signal description

Signal name Description
CLK_I Wishbone clock signal
RST_I Wishbone reset signal
CYC_I Wishbone cycle signal. High value frames blocks of access
STB_I Wishbone strobe signal. High value indicates cycle to this particular device
WE_I Wishbone write enable signal. High indicates data flowing from master to slave
ACK_O Wishbone acknowledge signal. High indicates that slave finished operation sucessfully
ACK_OI WhisboneTK acknowledge chain input signal
SEL_I(bus_width/8-1..0) Wishbone byte-selection signals
ADR_I(addr_width*-1..0) Wishbone address bus signals
DAT_I(bus_width-1..0) Wishbone data bus input (to slave direction) signals
DAT_O(bus_width-1..0) Wishbone data bus output (to master direction) signals
DAT_OI(bus_width-1..0) WhisboneTK data bus chain input signal
RST_VAL(width-1..0) Value written to the register upon reset
Q(width-1..0) Output value of the register

* addr_with: size2bits((width+offset+bus_width-1)/bus_width)-1.

Author & Maintainer

Andras Tantos