Project Name: OCIDEC (OpenCores IDE Controller)

Description:

ATA (AT attachment) interface core, also known as the IDE (Integrated Drive Electronics) interface.
The ATA interface provides a simple interface to (low cost) non-volatile memories, like harddisk drives, DVD players, CD(ROM) players/writers and CompactFlash and PC-CARD devices.

Development goals:

The development of a range of software and function backward compatible cores with a growing set of features. Software can detect which version of the core is implemented by reading the Device-ID and Revision-Number from the status register, thus making it possible to use a single device driver to handle all cores. This gives designers/system integraters the ability to trade off complexity/resource usage to available feature set/performance. All cores are designed according to the latest ATA/ATAPI specs.

Currently three cores are available:

Device	OCIDEC-1
Features	Smallest core. PIO transfer support only. Single timing register for all accesses to the connected devices.
Intended use	Single PIO only devices (PC-CARDs, CompactFlash). Designs requiring ATA capabilities, without the need for a complex feature set.
Gate usage	Approximately 4Kgates.

Device	OCIDEC-2
Features	Small core. PIO transfer support only. Common timing register for all compatible accesses to the connected devices. Separate timing register per device for fast DataPort accesses.
Intended use	Dual PIO only devices (PC-CARDs, CompactFlash). Designs requiring fast ATA capabilities, without DMA transfers.
Gate usage	Approximately 4.6Kgates.

Device	OCIDEC-3
Features	PIO, Single-Word DMA and Multi-Word DMA transfer support. Common timing register for all PIO compatible accesses to the connected devices. Separate timing registers per device for fast PIO DataPort accesses. Separate timing registers per device for DMA transfers. PIO write access ping-pong. WISHBONE Retry cycles for PIO accesses while controller busy.
Intended use	High speed ATA devices (Hard disks, CDROMs) Designs requiring full featured ATA capabilities.
Gate usage	Approximately 14Kgates.

All cores feature a WISHBONE rev.B2 compliant interface, but can be addapted for any other kind of bus easy.
See the on-line documentation for more information. Note: This is a preliminary version. No official release.

Current Status:

Three cores are available in VHDL and Verilog from OpenCores CVS via cvsweb or via cvsget.
ToDo:

Write documentation
Start development of OCIDEC-4, featuring UltraDMA support

Author & Maintainer(s):

Richard Herveille

Mailing-list:

cores@opencores.org_NOSPAM