Multiprocessor/Low-Level Support
- Completely reworked the user-access fault code
- Take the performance penalty only on error
- SMP locks relaxed for key operations:
- Separate IO request locks for interrupts
- Separate task and signal locks for the scheduler
- Full support for the IOAPIC controller
- Share the interrupt load over the entire machine
- Demonstrated scaling to 16+ cpus!
Notes:
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