[pci] configuration cycles

[Juanjo Garcés <juanjixx@hotmail.com>]

Hi everybody,

I've taken a look to the pci-bridge for a few weeks, but i don't still 
understand through where are done the configuration cycles from the 
wb_slave.v to pci_master_32.v?particulary the read configuration cycles.

Where comes the data in a read configuration cycle through?

I guess that the data is requested with a read configuration cycle(state 
S_CONF_READ from wb_slave) and the FSM respond with a retry, but then when 
the data is available, the S_CONF_READ doesn't make any read from the FIFO 
so i guess
-either the data doesn't come through the fifos with a configuration cycle 
read command,
-or the data come through the fifos but it has to be read with a normal 
delayed read command.
-or maybe there's something else i haven't considered...

I hope that I've made me understandable and also that someone can help me,

thanks,

Juanjo.

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