Re: [pci] TOP.v to TOP.sch

[Marco Buffa <marcobuffa@lombardiacom.it>]

Matt Schulte ha scritto:
> Does anyone know if Xilinx's ISE will let you do this?  Can I write a vhdl 
> module, turn it into a package and then connect it up to the verilog pci 
> project?
If you use FPGA Express, supported only by old versions of ISE (4.1 
should work), you can do that directly, without using the "package step".
With XST, you MUST use the package step, 'cause XST doesn't support 
mixed projects :-(

Regards.
-- 
Marco (Politecnico di Milano, Italy) FZS600'01

"Qui se accendessero le luci e riabbassassero le luci
ci troverebbero tutti in piedi con gli occhi aperti, qui"
(Ivano Fossati, "Sigonella")

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