[pci] clocking question

[ja21mme2@ya400.c0im]

I'd like to use different wishbone clocks for the wishbone slave module 
and the pci target module.  I have them on separate wb busses in my 
design, so it looks like I can do that.  Does anyone see anything I might 
have missed in the code that would prevent that from working?  It 
would be some kind of a dependency or shared hardware between the 
core's master and slave functions, and it would be on the wishbone-side 
of the clock synchronization logic.

j.
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