[pci] PCI Target State Machine

[naveenk23@yahoo.com]

Hi all
        I am having some clarifications on PCI Target State Machine on 
page 252 on PCI Specs..
        1. How to generate hit and D_done?
         2. On B_BUSY state, what happens if there is a hit on address 
decode and FRAME# is deasserted?
          3. I think TRDY, STOP and DEVSEL should be the outputs of the 
state machine. On which states and on what conditions, should they be 
generated. Like suppose if we are in S_DATA, must TRDY, DEVSEL, 
STOP need to be asserted?
          4. I think the state machine is in complex terminology? Could any 
one explain it in some simple terms with all the PCI related signals, when 
and how they need to be generated?
Please Reply soon,
Thanks in Advance
Naveen
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